The present invention generally relates to a data processing processor, and more specifically, relates to a data processing processor containing a bus arbitrating apparatus capable of selecting one channel with respect to bus access requests issued from a plurality of channels.
Conventionally, as a bus arbitration control scheme for selecting one apparatus in response to bus use requests issued from a plurality of apparatuses to allow the selected apparatus to use the bus, one conventional bus arbitration control system is described in JP-A-3-263158. FIG. 3 schematically shows a major arrangement of this conventional bus arbitration control system. That is, as shown in FIG. 3, an information processing apparatus is arranged by a bus 51 used to commonly transfer information; at least two sets of apparatuses having bus control functions, for example, bus masters such as a central processing unit 52, and input/output control apparatuses 53/54; and a bus arbitration control apparatus 55. The bus arbitration control apparatus 55 of this conventional information processing apparatus owns such a control function. That is, in this conventional information processing apparatus, at least one timer 56, 57, 58, and a storage unit for storing thereinto an initial value of this timer are provided every bus master in the bus arbitration control apparatus 55. The bus acquisition waiting allowable time for each of the bus masters is stored in each of the storage units. When bus use requests are notified from the bus masters to the bus arbitration control apparatus 55, the count-down operations of the timers 56, 57, 58, for the relevant bus masters are commenced. When the bus is brought into usable condition, in such a case that at least two bus use requests are issued from the bus masters, while the respective timer values for the bus masters are compared with each other, this bus arbitration control apparatus 55 allows such a bus master having a minimum count value of a timer to use the bus, and also stops the count-down operation of the timer for the bus master which is allowed to use the bus so as to return the count value to the initial value. As a result, the bus use priority degrees for the respective bus masters are automatically increased in connection with such a fact that the bus acquisition waiting time of the respective bus masters is prolonged, so that the bus arbitration suitable for the respective bus masters can be controlled in a proper manner.
In the above-described conventional bus arbitration control scheme, since the value of the timer is counted down until the base use permission is given to the bus master which has issued the bus use request, when such a bus master which has been once connected to the bus again issues the buss access request, this bus master is positioned to the lowest priority order, or the priority order nearly equal to this lowest priority order. As to this point, such an example that two bus masters issue bus use requests will now be simply explained with reference to FIG. 4.
In FIG. 4, it is so assumed that symbol xe2x80x9cTAxe2x80x9d shows a timer of a bus master xe2x80x9cAxe2x80x9d having a high priority order, symbol xe2x80x9cTBxe2x80x9d indicates a timer of a bus master xe2x80x9cBxe2x80x9d having a low priority order, and initial set values of the respective timers xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d are selected to xe2x80x9cTa0xe2x80x9d and xe2x80x9cTb0.xe2x80x9d It is also assumed that at a time instant xe2x80x9ct0xe2x80x9d, the count-down operations of these timers TA and TB are commenced in response to the bus use requests issued from the bus masters xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d, and at a time instant xe2x80x9ct1xe2x80x9d, the bus is brought into the usable condition. At this time, since values xe2x80x9cTa1xe2x80x9d and xe2x80x9cTb1xe2x80x9d of the respective timers TA and TB own such a relationship of Ta1 less than Tb1, the bus arbitration control apparatus issues the bus use permission with respect to the bus master A having the high priority order, and resets the value of the timer TA to the initial value xe2x80x9cTa0.xe2x80x9d On the other hand, the count-down operation of the timer TB of the bus master B having the low priority order is continued.
Furthermore, the following assumption is made. That is, before the bus use permission is issued to the bus master B, the bus master A again issues the bus use request and the timer TA starts the count-down operation at a time instant xe2x80x9ct2xe2x80x9d, and thereafter, the bus is brought into the usable condition at another time instant xe2x80x9ct3.xe2x80x9d In this case, values xe2x80x9cTa3xe2x80x9d and xe2x80x9cTb3xe2x80x9d of the respective timers TA and TB become such a relationship of Ta3 greater than Tb3 at the time instant xe2x80x9ct3.xe2x80x9d That is, since the relationship of Ta3 greater than Tb3 is reversed with respect to the above-described relationship of Ta1 less than Tb1, although the bus master A having the high priority order issues the bus use request, the bus arbitration control apparatus would issue the bus use permission with respect to the bus master B having the low priority order.
As a result, when the above-explained conventional bus arbitration control scheme is applied to such a data processing processor having a plurality of channels and capable of processing image data, although such a channel having a high necessity of a real-time processing operation issues a bus use request, the bus arbitration control apparatus allows another channel having a low necessity of a real-time processing operation to use the bus. Accordingly, this conventional bus arbitration control scheme has such a problem that the image data processing operation would fail.
As a consequence, an object of the present invention is to provide a data processing processor equipped with a bus arbitration apparatus. This bus arbitration apparatus is operated in such a manner that while a channel having a high necessity or a high priority order of a real-time processing operation issues a bus use request, this bus arbitration apparatus does not allow another channel having a low necessity or a low priority order of a real-time processing operation to use the bus.
It should be noted in this specification that such an interface portion provided in the data processing processor is referred to as a xe2x80x9cchannel.xe2x80x9d This xe2x80x9cchannelxe2x80x9d may interface between an external storage apparatus such as a DRAM and an SDRAM (synchronous DRAM) into which process data is stored, and a peripheral apparatus for transmitting/receiving data via a bus between this data processing processor and the own peripheral apparatus. For instance, in such a data processing processor for processing image data, the following units employed in the data processing processor will be referred to as xe2x80x9cchannelsxe2x80x9d hereinafter, namely, an interface unit for interfacing between a host CPU and the own data processing processor, a video input unit for capturing an MPEG (Moving Picture Coding Experts Group) image and an external input image, a display unit for synthesizing the images with each other to output the synthesized image to an external unit, and the like.
To solve the above-explained problem, a data processing apparatus, according to the present invention, is featured in that in a data processing processor having a bus arbitration apparatus for selecting one channel in response to bus use requests issued from a plurality of channels to thereby allow this selected channel to use the bus, the bus arbitration apparatus is comprised of:
a timer for changing count time in the case that a bus use request is notified to a channel having a high necessity of a real-time processing operation, namely a timer for counting down, or counting up a count value of the timer; and
a register for setting the count time of said timer with respect to a channel having a low necessity of a real-time processing operation, namely a register for setting a value larger than a maximum value of the count time in the case of the timer for counting down the count value thereof, or for setting a value smaller than a minimum value of the count time in the case of the timer for counting up the count value thereof; and
the bus arbitration apparatus executes a bus arbitration by comparing the values of the respective timers with the values of the register and by controlling to allow the channel having the small value to use the bus when the timer counts down the count value, and by controlling to allow the channel having the large value to use the bus when the timer counts up the count value of the timer.
Also, in the above-described data processing processor, instead of the register employed in the bus arbitration apparatus, such a timer for stopping a count change based upon a value larger than, or smaller than an initial value of the count value of the timer with respect to the channel having the high necessity of the real-time processing operation may be provided with respect to the channel having the low necessity of the real-time processing operation.
Also, the data processing processor is arranged by a CPU interface unit used to transmit/receive a signal between a host CPU and the own data processing processor; an image processing unit for processing an on-screen display operation and a 2-dimensional graphic calculating operation; a video input unit for capturing an external input image; a display unit for synthesizing images with each other to output a synthesized image to an external unit; and a memory interface unit used to transmit/receive a signal between an external storage apparatus and the own data processing processor. In this data processing processor, in such a case that the bus arbitration apparatus is provided in the memory interface unit, the above-explained channel having the high necessity of the real-time processing operation corresponds to the respective channels of the CPU interface unit, the image processing unit, and the display unit, whereas the channel having the low necessity of the real-time processing operation corresponds to the respective channels of the video input unit, and the memory interface unit.
Also, the external storage apparatus is either a DRAM or an SDRAM. Preferably, a refresh operation requesting circuit may be provided in the memory interface unit. This refresh operation requesting circuit produces such a request signal used to execute the refreshing operation of either the DRAM or the SDRAM for a time period during which the display unit does not request the use of the bus.
Also, the bus corresponds to such a data bus connected between the external storage apparatus and the memory interface unit. This data bus may be connected via the memory interface unit having the bus arbitration apparatus to the respective channels.
A data processing processor, according to the present invention, is featured in that in a data processing processor having a bus arbitration apparatus for selecting one channel in response to bus use request issued from a plurality of channels to thereby allow this selected channel to use the bus, the bus arbitration apparatus is comprised of:
a timer for changing a timer count value in the case that a bus use request is notified to a channel having a high priority order, namely a timer for counting down, or counting up a count value thereof; and
a register for setting a value larger than a maximum value of the count time, or for setting a value smaller than a minimum value of the count time with respect to a channel having a low priority order. The bus arbitration apparatus executes a bus arbitration control operation by comparing the values of the respective timers with the values of the register and controlling to allow the channel having the small value (or large value) as a result of the comparison to use the bus.
Also, in the above-described data processing processor, instead of the register employed in the bus arbitration apparatus, such a timer for stopping a count change based upon a value larger than, or smaller than an initial value of the count time of the timer provided with the channel having the high priority order may be provided with respect to the channel having the low priority order.
Other objects, features, and advantages of the present invention will become apparent from the description of the following embodiments of the present invention taken in conjunction with the accompanying drawings.